Difference between revisions of "Xeltek"

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The 5000E is internally composed of an 8 board stack. From top to bottom, the boards are:
 
The 5000E is internally composed of an 8 board stack. From top to bottom, the boards are:
  
- GND DRV
+
* GND DRV
- V3 DRV
+
* V3 DRV
- V3 (P1-72) DRV
+
* V3 (P1-72) DRV
- V1 DRV
+
* V1 DRV
- V2 DRV
+
* V2 DRV
- IO BOARD
+
* IO BOARD
- MCU BOARD
+
* MCU BOARD
- POWER BOARD
+
* POWER BOARD
  
 
=== Voltage Pin Driver Boards ===
 
=== Voltage Pin Driver Boards ===

Revision as of 06:57, 18 May 2018


Superpro and such

5000E

Hardware

The 5000E is internally composed of an 8 board stack. From top to bottom, the boards are:

  • GND DRV
  • V3 DRV
  • V3 (P1-72) DRV
  • V1 DRV
  • V2 DRV
  • IO BOARD
  • MCU BOARD
  • POWER BOARD

Voltage Pin Driver Boards

The V1/V2/V3* and GND drive boards share a similar topology. A set of shift registers is used to configure a transistor high or low-side drive. The GND board has two additional relays on pins, possibly for support of some high current device. The V1, V2 and V3 boards use a 74HC4094 shift reg, a ULN2003 transistor array and a high-side transistor to switch the voltage. The V2 and V3 boards incorporate a diode to prevent reverse biasing of the transistor which suggests the V1 voltage is the highest voltage used.

IO Board

The IO board is just a Spartan XC2S50E FPGA connected to each IO line through a 220 ohm resistor and a diode voltage clamp. Whether the I/O voltage tracks one of the supplies (V3?) is unknown.

MCU Board

Components:

  • AT91R40008 Processor (ARM7, no rom, very few peripherals, external bus interface)
  • TLC7226 Quad DAC
  • EN29LV040A Flash (512kB)
  • "Xeltek AE81" (Almost certainly an OTP FPGA)
  • USB Device controller (part # unreadable in photos)

Power Board

  • 3x LM317 + 3x MC34063 switchers
  • Topology not yet reversed
  • Misc op amps

Software

A basic bootloader / USB loader is resident in the on-board flash. The Host software communicates with this USB loader and downloads the actual programming routines into SRAM.