User:Robertbaruch

Staging ground

ATF22V10C

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:

• I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
• Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

Atmel Datasheet rev Jul 2010, see [1] for page 9 without the diagram cut off.

Lattice Datasheet rev Mar 1998.

The best view of the fuses is shown in page 5 of the Lattice datasheet, showing 5892 fuses.

The fuses are numbered as follows:

• 0-43: product term for asynchronous reset
• 44-439: sum of 8 product terms for output logic block 0
• 440-923: sum of 10 product terms for output logic block 1
• 924-1495: sum of 12 product terms for output logic block 2
• 1496-2155: sum of 14 product terms for output logic block 3
• 2156-2903: sum of 16 product terms for output logic block 4
• 2904-3651: sum of 16 product terms for output logic block 5
• 3652-4311: sum of 14 product terms for output logic block 6
• 4312-4883: sum of 12 product terms for output logic block 7
• 4884-5367: sum of 10 product terms for output logic block 8
• 5368-5763: sum of 8 product terms for output logic block 9
• 5764-5807: product term for synchronous preset
• 5808-5827: OLMC control fuses, 2 each, for output logic blocks
• 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

Enable programming mode

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

• pin 2(3): PRogramming ENable
• pin 13(16): -STRobe
• pin 3(4): WRite
• pins 4(5), 6(7), 7(9), and 9(11): ERase
• pin 8(10): OLMC data
• pin 11(13): Serial IN
• pin 14(17): Serial OUT
• pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

Disabling programming mode

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

Erasing the chip

Erasing the chip sets all fuses to the 1 state.

Writing a column

Writing a column of data involves:

• Sending the 132 bits of data serially, most significant bit first. When writing column 0x2C (the user data column), write the 64 bits of data first, then 68 bits of zero padding.
• Sending the 6-bit column address serially. most significant bit first.
• Setting WR high.
• Strobing the -STR line.
• Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

Reading a column

Reading a column of data involves:

• Sending the 6-bit column address serially. most significant bit first.
• Strobing the -STR line.
• Reading 132 bits of data serially, most significant bit first. When reading column 0x3A (the ID column), only 72 bits need to be read. When reading column 0x2C (the user data column), only 64 bits need to be read.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between SCLK and SOUT edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.