XGecu Protocol - Revision history

Drh: Add OVC documentation to logic tests.

2025-04-06T14:20:36Z

Add OVC documentation to logic tests.

← Older revision		Revision as of 14:20, 6 April 2025
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	====== 0x28 LOGIC_IC_TEST_VECTOR (t48) ======		====== 0x28 LOGIC_IC_TEST_VECTOR (t48) ======
	send 28 vv pp 00 n1 n2 n3 n4 [test vector]		send 28 vv pp 00 n1 n2 n3 n4 [test vector]
	recv 28 00 pp 00 00 00 00 00 [test reply]		recv 28 xx pp 00 00 00 00 00 [test reply]

	Performs a logic test.</br>		Performs a logic test.</br>
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	according to the test vector, it also resets all ISP pins to input. If N is non-zero the VCC voltage setting is ignored,		according to the test vector, it also resets all ISP pins to input. If N is non-zero the VCC voltage setting is ignored,
	VCC and GND are not reassigned, ISP values are unchanged. Pullups or pulldowns are still set according to vv&0x80.</br>		VCC and GND are not reassigned, ISP values are unchanged. Pullups or pulldowns are still set according to vv&0x80.</br>


	'''[test vector]''' consists of 24 bytes of which only the first pp/2 are significant. Each nyble corresponds to		'''[test vector]''' consists of 24 bytes of which only the first pp/2 are significant. Each nyble corresponds to
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	The test vector will silently allow VCC and GND assignments to pins which do not support it.</br>		The test vector will silently allow VCC and GND assignments to pins which do not support it.</br>
	By keeping the sequence number non-zero VCC voltages can be set to values not normally supported by logic test. ISP settings can also be retained.</br>		By keeping the sequence number non-zero VCC voltages can be set to values not normally supported by logic test. ISP settings can also be retained.</br>
	The pin numbers in the test vector and response are the pins of the inserted IC: not the pin numbers of the ZIF socket.		The pin numbers in the test vector and response are the pins of the inserted IC: not the pin numbers of the ZIF socket.</br>

			xx is normally 00 if it is 01 then overcurrent protection was triggered when performing the test.

	====== 0x29 AUTO_FIND (t48) ======		====== 0x29 AUTO_FIND (t48) ======

Drh: Add OVC documentation to READ_PINS

2025-04-06T12:15:38Z

Add OVC documentation to READ_PINS

← Older revision		Revision as of 12:15, 6 April 2025
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	====== 0x35 READ_PINS (t48) ======		====== 0x35 READ_PINS (t48) ======
	send 35 00 00 00 00 00 00 00		send 35 00 00 00 00 00 00 00
	recv 35 00 00 00 00 00 00 00 aa bb cc dd ee ff gg 00		recv 35 xx 00 00 00 00 00 00 aa bb cc dd ee ff gg 00
	Reads pins and returns bits for all 56 pins on aa bb cc dd ee ff gg		Reads pins and returns bits for all 56 pins on aa bb cc dd ee ff gg
	<br/>		<br/>
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	<br/>		<br/>
	J12 is internally connected to ZIF pin 21.		J12 is internally connected to ZIF pin 21.
			<br/>
			xx should be 00 if it is 01 then overcurrent protection has been triggered.

	====== 0x36 SET_OUT (t48) ======		====== 0x36 SET_OUT (t48) ======

Drh: AUTO_FIND also supported by TL866II+

2024-10-25T13:36:55Z

AUTO_FIND also supported by TL866II+

← Older revision		Revision as of 13:36, 25 October 2024
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	\|AUTO_FIND		\|AUTO_FIND
	\|		\|
	\|		\|0x29
	\|0x29		\|0x29
	\|		\|

Drh at 12:48, 25 October 2024

2024-10-25T12:48:47Z

← Older revision		Revision as of 12:48, 25 October 2024
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	\|0x3e		\|0x3e
	\|-		\|-
	\|~~?? autofind ??~~		\|AUTO_FIND
	\|		\|
	\|		\|
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	By keeping the sequence number non-zero VCC voltages can be set to values not normally supported by logic test. ISP settings can also be retained.</br>		By keeping the sequence number non-zero VCC voltages can be set to values not normally supported by logic test. ISP settings can also be retained.</br>
	The pin numbers in the test vector and response are the pins of the inserted IC: not the pin numbers of the ZIF socket.		The pin numbers in the test vector and response are the pins of the inserted IC: not the pin numbers of the ZIF socket.

			====== 0x29 AUTO_FIND (t48) ======
			send 29 00 00 00 00 00 00 00
			recv 29 00 pp 00 00 00 00 00 [pins]

			Attempt to detect which pins are active in the ZIF socket. This is used by logic tests when the "Auto Find" button is clicked.
			pp is the number of pins checked and is always 40 (0x28). '''[pins]''' is a list of pp pins one pin per byte. If the corresponding
			byte is set to 1 then the pin is active, 0 otherwise.

	====== 0x2d RESET_PIN_DRIVERS (t48) ======		====== 0x2d RESET_PIN_DRIVERS (t48) ======

Drh: Typo

2024-10-23T14:12:48Z

Typo

← Older revision		Revision as of 14:12, 23 October 2024
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	A pin can be tested for high impedance (tri-state) by performing the same test twice: once with pullup and the second time		A pin can be tested for high impedance (tri-state) by performing the same test twice: once with pullup and the second time
	with pulldown. If the pin changes from 0 ~~to 1~~ it is tri-state otherwise the pin is driving it.</br>		with pulldown. If the pin changes from 1 to 0 it is tri-state otherwise the pin is driving it.</br>

	The test vector will silently allow VCC and GND assignments to pins which do not support it.</br>		The test vector will silently allow VCC and GND assignments to pins which do not support it.</br>

Drh: Typo

2024-09-21T16:20:53Z

Typo

← Older revision		Revision as of 16:20, 21 September 2024
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	\|}		\|}

	====== 0x28 ~~LOGIC_TEST_VECTOR~~ (t48) ======		====== 0x28 LOGIC_IC_TEST_VECTOR (t48) ======
	send 28 vv pp 00 n1 n2 n3 n4 [test vector]		send 28 vv pp 00 n1 n2 n3 n4 [test vector]
	recv 28 00 pp 00 00 00 00 00 [test reply]		recv 28 00 pp 00 00 00 00 00 [test reply]

Drh at 16:14, 21 September 2024

2024-09-21T16:14:13Z

@@ Line 308: / Line 308: @@
+|
 |}
 ====== 0x2d  RESET_PIN_DRIVERS (t48) ======

Drh: Document RESET_PIN_DRIVERS

2024-09-21T15:18:19Z

Document RESET_PIN_DRIVERS

← Older revision		Revision as of 15:18, 21 September 2024
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	\|		\|
	\|}		\|}

			====== 0x2d RESET_PIN_DRIVERS (t48) ======
			send 2d 00 00 00 00 00 00 00
			Reset all pins state: set all pins to input, remove any GCC/VCC/VPP assignment,
			remove pullups and set VPP/VPP/VCCIO voltages to defaults.

	====== 0x2E SET_VCC_PIN (and voltage) (t48) ======		====== 0x2E SET_VCC_PIN (and voltage) (t48) ======

Drh: Add VCC/VPP/VCCIO defaults and not pullup/pulldown doesn't reset some VCC/VPP/GND assignment.

2024-09-21T14:48:33Z

Add VCC/VPP/VCCIO defaults and not pullup/pulldown doesn't reset some VCC/VPP/GND assignment.

← Older revision		Revision as of 14:48, 21 September 2024
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	xx bits 0 and 1 enables VCC on ISP-connector J13/J14.		xx bits 0 and 1 enables VCC on ISP-connector J13/J14.
	<br/>		<br/>
	zz is VCC voltage 01 to 3F. 00 means don't set VCC.		zz is VCC voltage 01 to 3F. 00 means don't set VCC. Default is 15.
	voltagemap_vcc[64]={ 0.0, 1.74, 1.83, 1.89, 2.00, 2.07, 2.18, 2.23,		voltagemap_vcc[64]={ 0.0, 1.74, 1.83, 1.89, 2.00, 2.07, 2.18, 2.23,
	2.32, 2.41, 2.45, 2.56, 2.65, 2.73, 2.79, 2.90,		2.32, 2.41, 2.45, 2.56, 2.65, 2.73, 2.79, 2.90,
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	<br/>		<br/>
	send 2f 01 00 00 00 00 00 00 xx 00 00 00		send 2f 01 00 00 00 00 00 00 xx 00 00 00
	Sets vpp voltage xx 00 to 3f from 9.31 to 25.16 volts, ca 0.25V per step.		Sets vpp voltage xx 00 to 3f from 9.31 to 25.16 volts, ca 0.25V per step. Default is 07.
	voltagemap_vpp[64]={ 9.31, 9.56, 9.83, 10.11, 10.32, 10.60, 10.87, 11.14,		voltagemap_vpp[64]={ 9.31, 9.56, 9.83, 10.11, 10.32, 10.60, 10.87, 11.14,
	11.32, 11.61, 11.86, 12.15, 12.35, 12.63, 12.90, 13.18,		11.32, 11.61, 11.86, 12.15, 12.35, 12.63, 12.90, 13.18,
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	<br/>		<br/>
	send 2f 02 00 00 00 00 00 00 xx 00 00 00		send 2f 02 00 00 00 00 00 00 xx 00 00 00
	Sets vccio voltage 00 to 04.		Sets vccio voltage 00 to 04, default is 03.
	voltagemap_vccio[5]={ 2.35, 2.47, 2.93, 3.23, 3.45 };		voltagemap_vccio[5]={ 2.35, 2.47, 2.93, 3.23, 3.45 };

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	====== 0x31 SET_PULLUPS (t48) ======		====== 0x31 SET_PULLUPS (t48) ======
	send 31 00 00 00 00 00 00 00		send 31 00 00 00 00 00 00 00
	Enable pull up for all pins and set all pins to input.		Enable pull up for all pins and set all pins to input. Any pins assigned to VPP/VCC/GND are unchanged.

	====== 0x32 SET_PULLDOWNS (t48) ======		====== 0x32 SET_PULLDOWNS (t48) ======
	send 32 00 00 00 00 00 00 00		send 32 00 00 00 00 00 00 00
	Enable pull down for all pins and set all pins to input.		Enable pull down for all pins and set all pins to input. Any pins assigned to VPP/VCC/GND are unchanged.

	====== 0x33 MEASURE_VOLTAGES (t48) ======		====== 0x33 MEASURE_VOLTAGES (t48) ======

Drh at 14:35, 21 September 2024

2024-09-21T14:35:53Z

← Older revision		Revision as of 14:35, 21 September 2024
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	writing 0x01 e.g. breaks reading voltages with cmd 0x33 but with 0x00 it still works.		writing 0x01 e.g. breaks reading voltages with cmd 0x33 but with 0x00 it still works.
	<br/>		<br/>
	xx ~~is 00 or 01 where 01~~ enables VCC on ISP-connector.		xx bits 0 and 1 enables VCC on ISP-connector J13/J14.
	<br/>		<br/>
	zz is VCC voltage 01 to 3F. 00 means don't set VCC.		zz is VCC voltage 01 to 3F. 00 means don't set VCC.
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	[ 31,30,10,9,4,3,2,1,32,33,34,36,37,38,39,40]		[ 31,30,10,9,4,3,2,1,32,33,34,36,37,38,39,40]
	<br/>		<br/>
	xx is 00 or 01 where 01 enables VPP on ISP-connector.		xx is 00 or 01 where 01 enables VPP on ISP-connector J1.
	<br/>		<br/>
	send 2f 01 00 00 00 00 00 00 xx 00 00 00		send 2f 01 00 00 00 00 00 00 xx 00 00 00
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	[8,7,6,5,4,3,2,1,16,15,14,13,12,11,10,9,32,31,30,29,27,25,20,18,40,39,38,37,36,35,34,33]		[8,7,6,5,4,3,2,1,16,15,14,13,12,11,10,9,32,31,30,29,27,25,20,18,40,39,38,37,36,35,34,33]
	<br/>		<br/>
	xx ~~is 00 or 01 where 01 enables~~ EGND on J6/J8/J16 on ISP-connector.		xx bits 0 through 2 enable EGND on J6/J8/J16 on ISP-connector.

	====== 0x31 SET_PULLUPS (t48) ======		====== 0x31 SET_PULLUPS (t48) ======