User:Robertbaruch - Revision history

Robertbaruch: /* Writing a column */

2018-05-21T01:22:46Z

Writing a column

← Older revision		Revision as of 01:22, 21 May 2018
Line 117:		Line 117:

	Writing a column of data involves:		Writing a column of data involves:
	* Sending the 132 bits of data serially, most significant bit first.		* Sending the 132 bits of data serially, most significant bit first. When writing column 0x2C (the user data column), write the 64 bits of data first, then 68 bits of zero padding.
	* Sending the 6-bit column address serially. most significant bit first.		* Sending the 6-bit column address serially. most significant bit first.
	* Setting WR high.		* Setting WR high.

Robertbaruch: /* Reading a column */

2018-05-21T01:21:37Z

Reading a column

← Older revision		Revision as of 01:21, 21 May 2018
Line 147:		Line 147:
	* Sending the 6-bit column address serially. most significant bit first.		* Sending the 6-bit column address serially. most significant bit first.
	* Strobing the -STR line.		* Strobing the -STR line.
	* Reading 132 bits of data serially, most significant bit first.		* Reading 132 bits of data serially, most significant bit first. When reading column 0x3A (the ID column), only 72 bits need to be read. When reading column 0x2C (the user data column), only 64 bits need to be read.

	Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!		Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

Robertbaruch: Reading a column

2018-05-21T01:13:26Z

Reading a column

← Older revision		Revision as of 01:13, 21 May 2018
Line 141:		Line 141:

	Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.		Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

			===Reading a column===

			Reading a column of data involves:
			* Sending the 6-bit column address serially. most significant bit first.
			* Strobing the -STR line.
			* Reading 132 bits of data serially, most significant bit first.

			Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

			<wavedrom>
			{
			signal: [
			{ name: "-STR", wave: "1......0.1..", node: ".......a.b" },
			{ name: "SIN", wave: "0333333..0...\|......", data: "c5 c4 c3 c2 c1 c0", phase: 0.5 },
			{ name: "SOUT", wave: "x........3333\|33330", data: "131 130 129 128 3 2 1 0" },
			{ name: "SCLK", wave: "lP....l...P..\|....l" },
			],
			edge: [
			"a<->b min 1µs",
			]
			}
			</wavedrom>

			Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between SCLK and SOUT edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

Robertbaruch: /* Writing a column */

2018-05-21T00:02:00Z

Writing a column

← Older revision		Revision as of 00:02, 21 May 2018
Line 132:		Line 132:
	{ name: "WR", wave: "0....\|.........1...0" },		{ name: "WR", wave: "0....\|.........1...0" },
	{ name: "SIN", wave: "03333\|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },		{ name: "SIN", wave: "03333\|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
	{ name: "SCLK", wave: "0P...\|.........0." },		{ name: "SCLK", wave: "lP...\|.........l." },
	],		],
	edge: [		edge: [

Robertbaruch: /* ATF22V10C */

2018-05-20T23:57:45Z

ATF22V10C

@@ Line 21: / Line 21: @@
 [https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].
-The best view of the fuses is shown in page 5 of the Lattice datasheet, showing 5892 fuses.
+The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.
-The fuses are organized as follows:
+The fuses are numbered as follows:
 * 0-43: product term for asynchronous reset
 * 44-439: sum of 8 product terms for output logic block 0
@@ Line 36: / Line 36: @@
 * 5368-5763: sum of 8 product terms for output logic block 9
 * 5764-5807: product term for synchronous preset
-* 5808-5827: control fuses, 2 each, for output logic blocks
+* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
 * 5828-5891: 8 bytes of programmable electronic signature data
 A security fuse is present, but its number is not in the datasheet.
 ===Enable programming mode===
 In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.
 * pin 2(3): PRogramming ENable
 * pin 13(16): -STRobe
@@ Line 49: / Line 56: @@
 * pins 4(5), 6(7), 7(9), and 9(11): ERase
 * pin 8(10): OLMC data
-Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation.
+Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.
 <wavedrom>
@@ Line 60: / Line 70: @@
      { name: "ER",    wave: "x0.." },
      { name: "OLMC",  wave: "x0.." },
    ],
    edge: [
@@ Line 66: / Line 79: @@
+}
 </wavedrom>

Robertbaruch at 23:11, 20 May 2018

2018-05-20T23:11:34Z

@@ Line 9: / Line 9: @@
    { name: "wire", wave: "0.1..0." },
 ]}
 </wavedrom>

Robertbaruch: Created page with "=Staging ground= ==wavedrom test== { signal: [ { name: "clk", wave: "p......" }, { name: "bus", wave: "x.34.5x", data: "head body tail" }, { name: "wire..."

2018-05-20T21:36:38Z

Created page with "=Staging ground= ==wavedrom test== <wavedrom> { signal: [ { name: "clk", wave: "p......" }, { name: "bus", wave: "x.34.5x", data: "head body tail" }, { name: "wire..."

New page

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>