Proghq - User contributions [en]

Talk:FOSS Programmer

2018-12-31T04:36:58Z

Robertbaruch: /* cr1901 */

= mcmaster =

While I'm not opposed to such a project, I'm skeptical of the time that it will take to develop such a device and the availability of it vs a COTS solution. In particular, with a TL866 costing $50 and still readily available, effort is much better spent focusing on these.

"Nominal max VPP is 21V on the TL866 A/CS and 18V on the TL866II." [Elemecca]. Did this cause any important devices to be discontinued?

= cr1901 =

While the TL866 is ending production, the TL866-II is still available/produced. In case TL866-II stops production and both variants become difficult to obtain easily, doing our own design has been proposed before. The short version is we have a lot of good/doable ideas for a FOSS programmer, but it ''would'' be a time commitment and would ''not'' be as cheap as a TL866. I suspect in principle an open design would attract more contributors in the long run; while Elemecca has done a great job on this front, PIC isn't exactly known to be pleasant to work with.

The basic idea I've seen thrown around for a FOSS programmer (from talking with davidc__ on siliconpr0n IRC channel) is thus:

* Use an FPGA with a custom I2C core, possibly an FPGA USB core as well. If we can tolerate HDL to provide a base that's rarely modified, this reduces part count while maximizing flexibility.
* The I2C interface talks to a number of Silego Greenpak 4s, which control both the pass transistors for the power lines and also provide lines of I/O for the target device.
* Greenpak 4 interfacing gives us "free 5V support", they are also incredibly cheap and small.
* FPGA can be put to other use? My proposal is a softcore (RISC-V? lm32? Something else?) running from SPIflash and using block RAM and RAM. This would give a superior development environment in terms of resources 'and' toolchain support compared to PIC.

:I like the idea of RISC-V on FPGA as a base, especially since gcc supports RISC-V now, as long as it uses a very popular FPGA. I'm a bit less enthusiastic about Greenpak -- mainly because I don't know anything about it. Like, are they in the habit of discontinuing chips older than like 5 years? --[[User:Robertbaruch|Robertbaruch]] ([[User talk:Robertbaruch|talk]]) 22:46, 29 December 2018 (UTC)

:[https://github.com/cliffordwolf/picorv32 picorv32] on a [https://www.digikey.com/products/en?keywords=LFE5U-25F LFE5U-25F] would probably be viable. The LFE5U-25F is already on the [https://tinyfpga.com/ TinyFPGA] EX prototypes, and is supported by [http://www.clifford.at/yosys/ yosys]. The sticky part is the pin driver: do we want all 40 pins capable of N types of voltages? We could just start with the drivers found in the TL866. As for USB, there are some [https://lcsc.com/search?q=ch340 very cheap FTDI alternatives] out there that could make USB easy. I've worked with FTDI chips, but I haven't tried the cheaper ones.

:My thought is that we could start small and easy: just use similar pin drivers to the TL866, use an Atmel ATMega as the main processor, add a cheap USB interface chip, and get a minimum viable product. Then start changing things out to support greater capabilities. --[[User:Robertbaruch|Robertbaruch]] ([[User talk:Robertbaruch|talk]]) 04:36, 31 December 2018 (UTC)

Talk:FOSS Programmer

2018-12-31T04:30:09Z

Robertbaruch: /* cr1901 */

= mcmaster =

While I'm not opposed to such a project, I'm skeptical of the time that it will take to develop such a device and the availability of it vs a COTS solution. In particular, with a TL866 costing $50 and still readily available, effort is much better spent focusing on these.

"Nominal max VPP is 21V on the TL866 A/CS and 18V on the TL866II." [Elemecca]. Did this cause any important devices to be discontinued?

= cr1901 =

While the TL866 is ending production, the TL866-II is still available/produced. In case TL866-II stops production and both variants become difficult to obtain easily, doing our own design has been proposed before. The short version is we have a lot of good/doable ideas for a FOSS programmer, but it ''would'' be a time commitment and would ''not'' be as cheap as a TL866. I suspect in principle an open design would attract more contributors in the long run; while Elemecca has done a great job on this front, PIC isn't exactly known to be pleasant to work with.

The basic idea I've seen thrown around for a FOSS programmer (from talking with davidc__ on siliconpr0n IRC channel) is thus:

* Use an FPGA with a custom I2C core, possibly an FPGA USB core as well. If we can tolerate HDL to provide a base that's rarely modified, this reduces part count while maximizing flexibility.
* The I2C interface talks to a number of Silego Greenpak 4s, which control both the pass transistors for the power lines and also provide lines of I/O for the target device.
* Greenpak 4 interfacing gives us "free 5V support", they are also incredibly cheap and small.
* FPGA can be put to other use? My proposal is a softcore (RISC-V? lm32? Something else?) running from SPIflash and using block RAM and RAM. This would give a superior development environment in terms of resources 'and' toolchain support compared to PIC.

:I like the idea of RISC-V on FPGA as a base, especially since gcc supports RISC-V now, as long as it uses a very popular FPGA. I'm a bit less enthusiastic about Greenpak -- mainly because I don't know anything about it. Like, are they in the habit of discontinuing chips older than like 5 years? --[[User:Robertbaruch|Robertbaruch]] ([[User talk:Robertbaruch|talk]]) 22:46, 29 December 2018 (UTC)

:[https://github.com/cliffordwolf/picorv32 picorv32] on a [https://www.digikey.com/products/en?keywords=LFE5U-25F LFE5U-25F] would probably be viable. The LFE5U-25F is already on the [https://tinyfpga.com/ TinyFPGA] EX prototypes, and is supported by [http://www.clifford.at/yosys/ yosys]. The sticky part is the pin driver: do we want all 40 pins capable of N types of voltages? We could just start with the drivers found in the TL866. As for USB, there are some [https://lcsc.com/search?q=ch340 very cheap FTDI alternatives] out there that could make USB easy. I've worked with FTDI chips, but I haven't tried the cheaper ones. --[[User:Robertbaruch|Robertbaruch]] ([[User talk:Robertbaruch|talk]]) 04:30, 31 December 2018 (UTC)

Talk:FOSS Programmer

2018-12-29T22:46:42Z

Robertbaruch: /* cr1901 */

User:Robertbaruch

2018-05-21T01:22:46Z

Robertbaruch: /* Writing a column */

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>

==ATF22V10C==

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:
* I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
* Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

[https://archive.org/details/ATF22V10CCQ Atmel Datasheet rev Jul 2010], see [http://proghq.org/wiki/File:ATF22V10_LOGIC_DIAGRAM.png] for page 9 without the diagram cut off.

[https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].

The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.

The fuses are numbered as follows:
* 0-43: product term for asynchronous reset
* 44-439: sum of 8 product terms for output logic block 0
* 440-923: sum of 10 product terms for output logic block 1
* 924-1495: sum of 12 product terms for output logic block 2
* 1496-2155: sum of 14 product terms for output logic block 3
* 2156-2903: sum of 16 product terms for output logic block 4
* 2904-3651: sum of 16 product terms for output logic block 5
* 3652-4311: sum of 14 product terms for output logic block 6
* 4312-4883: sum of 12 product terms for output logic block 7
* 4884-5367: sum of 10 product terms for output logic block 8
* 5368-5763: sum of 8 product terms for output logic block 9
* 5764-5807: product term for synchronous preset
* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
* 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

===Enable programming mode===

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

* pin 2(3): PRogramming ENable
* pin 13(16): -STRobe
* pin 3(4): WRite
* pins 4(5), 6(7), 7(9), and 9(11): ERase
* pin 8(10): OLMC data
* pin 11(13): Serial IN
* pin 14(17): Serial OUT
* pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x1..", node: ".a.." },
{ name: "PREN", wave: "0.1.", node: "..b.c" },
{ name: "WR", wave: "x0.." },
{ name: "ER", wave: "x0.." },
{ name: "OLMC", wave: "x0.." },
{ name: "SIN", wave: "x0.." },
{ name: "SOUT", wave: "x0.." },
{ name: "SCLK", wave: "x0.." },
],
edge: [
"a<->b min 20µs", "b<->c min 50ms"
]
}
</wavedrom>

===Disabling programming mode===

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x..." },
{ name: "PREN", wave: "1.0.", node: "..a.b" },
],
edge: [
"a<->b min 20µs",
]
}
</wavedrom>

===Erasing the chip===

Erasing the chip sets all fuses to the 1 state.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1.0.1.", node: "..a.b" },
{ name: "WR", wave: "01...0" },
{ name: "ER", wave: "01...0" },
{ name: "OLMC", wave: "01...0" },
],
edge: [
"a<->b min 200ms",
]
}
</wavedrom>

===Writing a column===

Writing a column of data involves:
* Sending the 132 bits of data serially, most significant bit first. When writing column 0x2C (the user data column), write the 64 bits of data first, then 68 bits of zero padding.
* Sending the 6-bit column address serially. most significant bit first.
* Setting WR high.
* Strobing the -STR line.
* Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1....|..........0.1.", node: "................a.b" },
{ name: "WR", wave: "0....|.........1...0" },
{ name: "SIN", wave: "03333|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SCLK", wave: "lP...|.........l." },
],
edge: [
"a<->b min 20ms",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

===Reading a column===

Reading a column of data involves:
* Sending the 6-bit column address serially. most significant bit first.
* Strobing the -STR line.
* Reading 132 bits of data serially, most significant bit first. When reading column 0x3A (the ID column), only 72 bits need to be read. When reading column 0x2C (the user data column), only 64 bits need to be read.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1......0.1..", node: ".......a.b" },
{ name: "SIN", wave: "0333333..0...|......", data: "c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SOUT", wave: "x........3333|33330", data: "131 130 129 128 3 2 1 0" },
{ name: "SCLK", wave: "lP....l...P..|....l" },
],
edge: [
"a<->b min 1µs",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between SCLK and SOUT edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

User:Robertbaruch

2018-05-21T01:21:37Z

Robertbaruch: /* Reading a column */

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>

==ATF22V10C==

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:
* I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
* Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

[https://archive.org/details/ATF22V10CCQ Atmel Datasheet rev Jul 2010], see [http://proghq.org/wiki/File:ATF22V10_LOGIC_DIAGRAM.png] for page 9 without the diagram cut off.

[https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].

The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.

The fuses are numbered as follows:
* 0-43: product term for asynchronous reset
* 44-439: sum of 8 product terms for output logic block 0
* 440-923: sum of 10 product terms for output logic block 1
* 924-1495: sum of 12 product terms for output logic block 2
* 1496-2155: sum of 14 product terms for output logic block 3
* 2156-2903: sum of 16 product terms for output logic block 4
* 2904-3651: sum of 16 product terms for output logic block 5
* 3652-4311: sum of 14 product terms for output logic block 6
* 4312-4883: sum of 12 product terms for output logic block 7
* 4884-5367: sum of 10 product terms for output logic block 8
* 5368-5763: sum of 8 product terms for output logic block 9
* 5764-5807: product term for synchronous preset
* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
* 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

===Enable programming mode===

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

* pin 2(3): PRogramming ENable
* pin 13(16): -STRobe
* pin 3(4): WRite
* pins 4(5), 6(7), 7(9), and 9(11): ERase
* pin 8(10): OLMC data
* pin 11(13): Serial IN
* pin 14(17): Serial OUT
* pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x1..", node: ".a.." },
{ name: "PREN", wave: "0.1.", node: "..b.c" },
{ name: "WR", wave: "x0.." },
{ name: "ER", wave: "x0.." },
{ name: "OLMC", wave: "x0.." },
{ name: "SIN", wave: "x0.." },
{ name: "SOUT", wave: "x0.." },
{ name: "SCLK", wave: "x0.." },
],
edge: [
"a<->b min 20µs", "b<->c min 50ms"
]
}
</wavedrom>

===Disabling programming mode===

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x..." },
{ name: "PREN", wave: "1.0.", node: "..a.b" },
],
edge: [
"a<->b min 20µs",
]
}
</wavedrom>

===Erasing the chip===

Erasing the chip sets all fuses to the 1 state.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1.0.1.", node: "..a.b" },
{ name: "WR", wave: "01...0" },
{ name: "ER", wave: "01...0" },
{ name: "OLMC", wave: "01...0" },
],
edge: [
"a<->b min 200ms",
]
}
</wavedrom>

===Writing a column===

Writing a column of data involves:
* Sending the 132 bits of data serially, most significant bit first.
* Sending the 6-bit column address serially. most significant bit first.
* Setting WR high.
* Strobing the -STR line.
* Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1....|..........0.1.", node: "................a.b" },
{ name: "WR", wave: "0....|.........1...0" },
{ name: "SIN", wave: "03333|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SCLK", wave: "lP...|.........l." },
],
edge: [
"a<->b min 20ms",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

===Reading a column===

Reading a column of data involves:
* Sending the 6-bit column address serially. most significant bit first.
* Strobing the -STR line.
* Reading 132 bits of data serially, most significant bit first. When reading column 0x3A (the ID column), only 72 bits need to be read. When reading column 0x2C (the user data column), only 64 bits need to be read.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1......0.1..", node: ".......a.b" },
{ name: "SIN", wave: "0333333..0...|......", data: "c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SOUT", wave: "x........3333|33330", data: "131 130 129 128 3 2 1 0" },
{ name: "SCLK", wave: "lP....l...P..|....l" },
],
edge: [
"a<->b min 1µs",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between SCLK and SOUT edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

User:Robertbaruch

2018-05-21T01:13:26Z

Robertbaruch: Reading a column

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>

==ATF22V10C==

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:
* I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
* Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

[https://archive.org/details/ATF22V10CCQ Atmel Datasheet rev Jul 2010], see [http://proghq.org/wiki/File:ATF22V10_LOGIC_DIAGRAM.png] for page 9 without the diagram cut off.

[https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].

The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.

The fuses are numbered as follows:
* 0-43: product term for asynchronous reset
* 44-439: sum of 8 product terms for output logic block 0
* 440-923: sum of 10 product terms for output logic block 1
* 924-1495: sum of 12 product terms for output logic block 2
* 1496-2155: sum of 14 product terms for output logic block 3
* 2156-2903: sum of 16 product terms for output logic block 4
* 2904-3651: sum of 16 product terms for output logic block 5
* 3652-4311: sum of 14 product terms for output logic block 6
* 4312-4883: sum of 12 product terms for output logic block 7
* 4884-5367: sum of 10 product terms for output logic block 8
* 5368-5763: sum of 8 product terms for output logic block 9
* 5764-5807: product term for synchronous preset
* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
* 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

===Enable programming mode===

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

* pin 2(3): PRogramming ENable
* pin 13(16): -STRobe
* pin 3(4): WRite
* pins 4(5), 6(7), 7(9), and 9(11): ERase
* pin 8(10): OLMC data
* pin 11(13): Serial IN
* pin 14(17): Serial OUT
* pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x1..", node: ".a.." },
{ name: "PREN", wave: "0.1.", node: "..b.c" },
{ name: "WR", wave: "x0.." },
{ name: "ER", wave: "x0.." },
{ name: "OLMC", wave: "x0.." },
{ name: "SIN", wave: "x0.." },
{ name: "SOUT", wave: "x0.." },
{ name: "SCLK", wave: "x0.." },
],
edge: [
"a<->b min 20µs", "b<->c min 50ms"
]
}
</wavedrom>

===Disabling programming mode===

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x..." },
{ name: "PREN", wave: "1.0.", node: "..a.b" },
],
edge: [
"a<->b min 20µs",
]
}
</wavedrom>

===Erasing the chip===

Erasing the chip sets all fuses to the 1 state.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1.0.1.", node: "..a.b" },
{ name: "WR", wave: "01...0" },
{ name: "ER", wave: "01...0" },
{ name: "OLMC", wave: "01...0" },
],
edge: [
"a<->b min 200ms",
]
}
</wavedrom>

===Writing a column===

Writing a column of data involves:
* Sending the 132 bits of data serially, most significant bit first.
* Sending the 6-bit column address serially. most significant bit first.
* Setting WR high.
* Strobing the -STR line.
* Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1....|..........0.1.", node: "................a.b" },
{ name: "WR", wave: "0....|.........1...0" },
{ name: "SIN", wave: "03333|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SCLK", wave: "lP...|.........l." },
],
edge: [
"a<->b min 20ms",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

===Reading a column===

Reading a column of data involves:
* Sending the 6-bit column address serially. most significant bit first.
* Strobing the -STR line.
* Reading 132 bits of data serially, most significant bit first.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1......0.1..", node: ".......a.b" },
{ name: "SIN", wave: "0333333..0...|......", data: "c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SOUT", wave: "x........3333|33330", data: "131 130 129 128 3 2 1 0" },
{ name: "SCLK", wave: "lP....l...P..|....l" },
],
edge: [
"a<->b min 1µs",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between SCLK and SOUT edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

User:Robertbaruch

2018-05-21T00:02:00Z

Robertbaruch: /* Writing a column */

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>

==ATF22V10C==

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:
* I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
* Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

[https://archive.org/details/ATF22V10CCQ Atmel Datasheet rev Jul 2010], see [http://proghq.org/wiki/File:ATF22V10_LOGIC_DIAGRAM.png] for page 9 without the diagram cut off.

[https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].

The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.

The fuses are numbered as follows:
* 0-43: product term for asynchronous reset
* 44-439: sum of 8 product terms for output logic block 0
* 440-923: sum of 10 product terms for output logic block 1
* 924-1495: sum of 12 product terms for output logic block 2
* 1496-2155: sum of 14 product terms for output logic block 3
* 2156-2903: sum of 16 product terms for output logic block 4
* 2904-3651: sum of 16 product terms for output logic block 5
* 3652-4311: sum of 14 product terms for output logic block 6
* 4312-4883: sum of 12 product terms for output logic block 7
* 4884-5367: sum of 10 product terms for output logic block 8
* 5368-5763: sum of 8 product terms for output logic block 9
* 5764-5807: product term for synchronous preset
* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
* 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

===Enable programming mode===

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

* pin 2(3): PRogramming ENable
* pin 13(16): -STRobe
* pin 3(4): WRite
* pins 4(5), 6(7), 7(9), and 9(11): ERase
* pin 8(10): OLMC data
* pin 11(13): Serial IN
* pin 14(17): Serial OUT
* pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x1..", node: ".a.." },
{ name: "PREN", wave: "0.1.", node: "..b.c" },
{ name: "WR", wave: "x0.." },
{ name: "ER", wave: "x0.." },
{ name: "OLMC", wave: "x0.." },
{ name: "SIN", wave: "x0.." },
{ name: "SOUT", wave: "x0.." },
{ name: "SCLK", wave: "x0.." },
],
edge: [
"a<->b min 20µs", "b<->c min 50ms"
]
}
</wavedrom>

===Disabling programming mode===

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x..." },
{ name: "PREN", wave: "1.0.", node: "..a.b" },
],
edge: [
"a<->b min 20µs",
]
}
</wavedrom>

===Erasing the chip===

Erasing the chip sets all fuses to the 1 state.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1.0.1.", node: "..a.b" },
{ name: "WR", wave: "01...0" },
{ name: "ER", wave: "01...0" },
{ name: "OLMC", wave: "01...0" },
],
edge: [
"a<->b min 200ms",
]
}
</wavedrom>

===Writing a column===

Writing a column of data involves:
* Sending the 132 bits of data serially, most significant bit first.
* Sending the 6-bit column address serially. most significant bit first.
* Setting WR high.
* Strobing the -STR line.
* Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1....|..........0.1.", node: "................a.b" },
{ name: "WR", wave: "0....|.........1...0" },
{ name: "SIN", wave: "03333|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SCLK", wave: "lP...|.........l." },
],
edge: [
"a<->b min 20ms",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

User:Robertbaruch

2018-05-20T23:57:45Z

Robertbaruch: /* ATF22V10C */

=Staging ground=

==wavedrom test==

<wavedrom>
{ signal: [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." },
]}
</wavedrom>

==ATF22V10C==

At some point prior to Jul 2010, Atmel decided to make their own 22V10. It is pin- and fuse-compatible with the Lattice GAL22V10, but with additional features:
* I/O pin-keeper circuits, holding the previous value of an input after the input goes high-impedance.
* Optional pin-controlled power-down mode. This mode is controlled by a fuse not present in the Lattice chip.

[https://archive.org/details/ATF22V10CCQ Atmel Datasheet rev Jul 2010], see [http://proghq.org/wiki/File:ATF22V10_LOGIC_DIAGRAM.png] for page 9 without the diagram cut off.

[https://archive.org/details/gal22v10 Lattice Datasheet rev Mar 1998].

The best view of the fuses is shown in [https://archive.org/stream/gal22v10#page/n3/mode/2up page 5 of the Lattice datasheet], showing 5892 fuses.

The fuses are numbered as follows:
* 0-43: product term for asynchronous reset
* 44-439: sum of 8 product terms for output logic block 0
* 440-923: sum of 10 product terms for output logic block 1
* 924-1495: sum of 12 product terms for output logic block 2
* 1496-2155: sum of 14 product terms for output logic block 3
* 2156-2903: sum of 16 product terms for output logic block 4
* 2904-3651: sum of 16 product terms for output logic block 5
* 3652-4311: sum of 14 product terms for output logic block 6
* 4312-4883: sum of 12 product terms for output logic block 7
* 4884-5367: sum of 10 product terms for output logic block 8
* 5368-5763: sum of 8 product terms for output logic block 9
* 5764-5807: product term for synchronous preset
* 5808-5827: OLMC control fuses, 2 each, for output logic blocks
* 5828-5891: 8 bytes of programmable electronic signature data

A security fuse is present, but its number is not in the datasheet.

Note that while the fuses are numbered as if they increment along a row, fuses are actually written one column at a time! There are 44 columns of data for the sum or products matrix, columns 0-43 (0x00-0x2B), each with 132 bits. Column 44 (0x2C) is for the programmable electronic signature and also contains 132 bits, although only the first 64 bits are valid.

There is a read-only column 58 (0x3A) containing 72 bits of chip signature data. This identifies the chip.

The 20 OLMC control fuses do not have a column address. Instead, they are "addressed" by a separate pin.

===Enable programming mode===

In programming mode, the following pins have alternate functions. Pin numbering is for the DIP/SOIC/TSSOP(PLCC) package.

* pin 2(3): PRogramming ENable
* pin 13(16): -STRobe
* pin 3(4): WRite
* pins 4(5), 6(7), 7(9), and 9(11): ERase
* pin 8(10): OLMC data
* pin 11(13): Serial IN
* pin 14(17): Serial OUT
* pin 10(12): Serial CLK

Programming mode is enabled by applying 12V to PREN. PREN must remain at 12V for at least 50 milliseconds before beginning any other operation, and must remain at 12V for all programming operations.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x1..", node: ".a.." },
{ name: "PREN", wave: "0.1.", node: "..b.c" },
{ name: "WR", wave: "x0.." },
{ name: "ER", wave: "x0.." },
{ name: "OLMC", wave: "x0.." },
{ name: "SIN", wave: "x0.." },
{ name: "SOUT", wave: "x0.." },
{ name: "SCLK", wave: "x0.." },
],
edge: [
"a<->b min 20µs", "b<->c min 50ms"
]
}
</wavedrom>

===Disabling programming mode===

Programming mode is disabled by allowing PREN to drop to 0V for at least 20 microseconds.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "x..." },
{ name: "PREN", wave: "1.0.", node: "..a.b" },
],
edge: [
"a<->b min 20µs",
]
}
</wavedrom>

===Erasing the chip===

Erasing the chip sets all fuses to the 1 state.

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1.0.1.", node: "..a.b" },
{ name: "WR", wave: "01...0" },
{ name: "ER", wave: "01...0" },
{ name: "OLMC", wave: "01...0" },
],
edge: [
"a<->b min 200ms",
]
}
</wavedrom>

===Writing a column===

Writing a column of data involves:
* Sending the 132 bits of data serially, most significant bit first.
* Sending the 6-bit column address serially. most significant bit first.
* Setting WR high.
* Strobing the -STR line.
* Setting WR low.

Warning: The serial protocol is very similar to, but not identical to, SPI. Data is clocked in on the positive edge of SCLK, but note that the very last bit is not clocked in by SCLK, but by the negative edge of -STR!

<wavedrom>
{
signal: [
{ name: "-STR", wave: "1....|..........0.1.", node: "................a.b" },
{ name: "WR", wave: "0....|.........1...0" },
{ name: "SIN", wave: "03333|3333333333.0", data: "131 130 129 128 3 2 1 0 c5 c4 c3 c2 c1 c0", phase: 0.5 },
{ name: "SCLK", wave: "0P...|.........0." },
],
edge: [
"a<->b min 20ms",
]
}
</wavedrom>

Note: SCLK frequency may be no higher than 500kHz. It is not known what the minimum time between WR and -STR edges are, but it is under 1 µs. It is also not known what the setup and hold times for SIN are.

User:Robertbaruch

2018-05-20T23:11:34Z

Robertbaruch:

File:ATF22V10 LOGIC DIAGRAM.png

2018-05-20T22:23:19Z

Robertbaruch: Page 9 of the Atmel ATF22V10C(Q) datasheet, without the diagram cut off.

Page 9 of the Atmel ATF22V10C(Q) datasheet, without the diagram cut off.

User:Robertbaruch

2018-05-20T21:36:38Z

Robertbaruch: Created page with "=Staging ground= ==wavedrom test== <wavedrom> { signal: [ { name: "clk", wave: "p......" }, { name: "bus", wave: "x.34.5x", data: "head body tail" }, { name: "wire..."